This invention relates to monitoring devices, and more particularly to a method and apparatus for determining the internal status of a processor without effecting the operational environment associated therewith.
Broadly speaking, a processor operates by sequentially performing a set of instructions, generally referred to as a program. The program is designed to accomplish an objective, and may reference additional information, generally referred to as data, in accomplishing the objective.
A processor may be considered as fundamentally comprising a central processing unit and a memory unit. The central processing unit basically performs desired operations pursuant to instructions and data which are stored in the associated memory unit. Typically the memory unit is comprised of many sequential unique storage locations, each of which is capable of storing a unit of information. In this regard, it should be particularly noted that the units of information stored in the memory may be either instructions to direct the operations of the central processing unit, or data which will be operated upon by the central processing unit pursuant to the instructions. As processors are complex devices, it is frequently desirable to monitor the operations of a processor, especially during the design and development of apparatus employing one or a plurality of processors. In the past this has been accomplished in a number of ways.
In one approach commonly used in central processing units constructed from discrete devices, the contents of various registers and the status of various operations which occur internal to the central processing unit are displayed by a collection of indicating devices. In some designs, each indicating device is permanently associated with a particular item of interest within the central processor, and would continuously display the associated information. This frequently results in a large collection of indicating devices of various types. Such an approach frequently further includes additional monitoring apparatus, such as instruction execution control devices. Such devices operate to provide such functions as controlling the rate at which the central processing unit performs the execution of individual instructions in a program, or halting the execution of instructions upon the occurrence of predefined conditions.
Approaches employing dedicated indicating and monitoring devices offer a number of advantages, the most significant of which provides the capability of monitoring the operation of the central processing unit without disturbing the environment in which a program may be executing. However, notwithstanding this advantage, the monitoring functions possible with such an approach are nevertheless somewhat limited. In particular, such an approach offers little detailed information regarding events which occur with respect to a program during the execution thereof. This situation becomes even more complex when a central processing unit must further respond to external events in addition to executing a particular program. In the past, this problem was addressed by the attachment of specialized monitoring equipment to the central processing unit. By way of example, if an analysis of the performance of a central processing unit in the execution of a particular program was of interest, the details of the particular program and associated parts of the central processing unit would be closely examined. In particular, the information of interest with respect to the program would first be determined. Thereafter, the associated portions within the central processor would be determined by a close examination of the internal architecture and operation of the central processor to determine the appropriate signals within the central processor which would contain the information of interest. Thereafter, signal probes would be attached to the points in the internal circuitry of the central processor to monitor the particular signals of interest. With the signal probes in place, the program of interest would then be run on the central processing unit, and the information of interest collected. The information received via the signal probes would then be processed according to the particular requirements of the monitoring task, and recorded for subsequent analysis. By subsequent analysis of the recorded information, the desired details with respect to the performance of the central processing unit in the performance of a particular program could be determined.
With the advent of the fabrication of central processing units as integrated circuits, and the accompanying limitations associated with integrated circuit packaging techniques, it has not been possible to use dedicated indicating and monitoring devices to monitor the internal operation of a central processing unit fabricated as an integrated circuit. This limitation primarily results from the physical constraint of being unable to route the large number of electrical conductors necessarily associated with dedicated indicating devices out of the integrated circuit package. With advances in the design of central processing units, the physical limitations imposed by integrated circuit packaging techniques have become even more limiting, and in some applications have operated to require multiplexing techniques to make the necessary signals available. This situation naturally makes the monitoring of the activities which occur internal to the central processing unit accordingly more difficult.
In response to the limitations imposed by integrated circuit packaging techniques, and the desire to monitor operations internal to a central processing unit, a number of alternate approaches have been taken. One such approach has been based upon hardware techniques, and a second approach has been based upon programming, or software techniques.
Generally speaking, the signals associated with a central processing unit fabricated as an integrated circuit can be broadly classified into three groups: control signals, address signals and data signals. These signals are used to electrically interface the central processing unit with the components associated therewith. Consequently, monitoring these signals can provide some indication of the fundamental operations occurring internally to the central processor unit. A number of techniques have been employed in the past based upon this approach.
In one approach, the address signals from the central processing unit are segregated into two groups, and each address signal present within each group is assigned a particular binary weight. Thereafter, a corresponding analog signal is derived for each of the signal groups having a magnitude proportional to the binary weight of the signal present on the address lines within each of the two groups. This is generally accomplished through the use of a digital-to-analog converter device. Thereafter, the two analog output signals are used to control the horizontal and vertical deflection plates of an oscilloscope. The resulting display on the oscilloscope will consequently provide some information with respect to the location in memory wherein the central processing unit is currently active. While such an approach does offer the advantage of not disturbing the operational environment within the central processing unit, the information so provided with respect to the internal operation of the central processing unit is very limited.
In yet another approach employing a visual monitoring device, each unique location in memory for a designated portion of memory is assigned a particular location on a visual monitoring device, and the contents of the associated memory location are displayed therein. Consequently, by observing the resulting visual display, it is possible to gain some insight regarding the activities of the central processor with respect to the memory.
The foregoing examples are but a few of the approaches which have been employed in the past to gain insight on the internal operations of a central processing unit by monitoring the various signals associated therewith. It will be observed that while each approach shares the common advantage of not disturbing the operation of a program within the central processing unit, the information provided by the monitoring technique has been somewhat limited, failing to provide comprehensive information relating to the internal operations of the central processing unit.
In yet a different approach to the monitoring problem, the central processing unit has been used to monitor itself. In such an approach, a series of programs are used to direct the central processing unit to monitor the contents of various registers and the status of events occurring internal to the central processing unit, and thereafter to report the results.
In one such approach the central processor operates under the control of a control program, often referred to as a "monitor program". Operating under the control of the monitor program, the central processing unit performs selected instructions present in the particular program of interest under the strict control of the operator of the central processing unit. In such an approach, it is possible for the operator to exercise greater control over the activities of the central processing unit than would otherwise be possible. Such control activities would normally include control over the execution of the sequence of instructions, e.g., executing instructions on a one-by-one basis, or executing instructions in groups. At any point in the execution process, it would be possible to monitor the internal state of the central processing unit, and report the status to the operator. Other control activities would include the ability to individually examine, and if necessary change, the contents of any location in the memory unit. By employing the approach of using the central processing unit to monitor itself, much greater control and monitoring of the activities of the central processing unit is possible. By using such an approach, the monitoring of parameters internal to the central processing unit is frequently limited only by the complexity of the monitor program itself.
However, notwithstanding the advantages presented by using the central processing unit to monitor itself, such an approach has an inherent shortcoming which is fundamental to the process. In particular, the basic environment existing during the execution of program instructions is disturbed. This follows from the fact that the central processing unit must not only execute the program of interest, but must also execute the monitor program. By so executing the monitor program, the central processing unit is performing tasks that it otherwise would not do if it were executing the program alone. Such a shortcoming can present disadvantages of varying scope. One such disadvantage is in the time required for the execution of the program of interest. Since the central processing unit is having to execute both the program of interest as well as the monitor program, additional execution time is clearly required. While they may be acceptable under some conditions, it can be most undesirable under others. In particular, in an application in which it is desired to monitor an environment wherein the central processing unit must not only execute a program of interest, but must also respond to events which are occurring external to the central processing unit, the imposing upon the central processing unit of the additional task of executing the monitor program can significantly alter the basic environment which is desired to be monitored. This result follows from the fact that the time which the central processing unit would otherwise dedicate to the program of interest and responding to events which are occurring external to the central processing unit is reduced by the amount of time required by the central processor to perform the appropriate portions of the monitor program. Consequently such an approach has the serious shortcomings of disturbing the environment which is desired to be monitored.
A yet further approach is taken with current logic analyzer type devices. In particular, signal probes associated with a logic analyzer are coupled to the signals produced by a microprocessor: the control signals, the address signals and the data signals. The logic analyzer then operates to monitor the foregoing signals, and can be further configured to indicate the occurrence of certain pre-defined conditions with respect to the signals monitored. In addition thereto, it is possible to determine the internal status of the monitored processor device through the use of a type of monitor program to effect a dump of the status of internal registers within the processor. This procedure is commonly referred to as "signal stepping" the processor, and consists of the execution of an associated dump routine. The dump routine consists of a group of instructions which must be executed after each instruction of the monitored program, and consequently seriously degrades the performance of the processor. In particular, such a procedure further completely disrupts the internal program execution environment within the processor, and makes it impossible to diagnose problems associated with real-time operation.
One approach currently taken to achieve visibility of the internal status of registers with the processor without disturbing the operating environment requires the reconstruction of the entire processor. This reconstructed processor is frequently fabricated with commonly available logic chips. While such an approach will provide the desired information without disturbing the internal operational environment, a number of serious shortcomings are unavoidable with such an approach. In particular, the discrete reconstructed version of the processor is necessarily fabricated on some type of circuit board, and consequently presents an environment of relatively high capacitance between connections of the logic elements. The charging and discharging of these capacitances with changes in the states of the associated logic signals results in a severe limitation on the maximum speed at which the reconstructed processor is capable of operating. This necessarily results in a lower maximum operating speed for the reconstructed processor. The lower operating speed naturally introduces an undesired operating condition for monitoring purposes.
A yet different approach likewise currently taken to achieve visibility of the internal status of registers within a processor without disturbing the operating environment requires the design of a second version of the processor providing bonding pads for the desired signals and register status. This technique is commonly referred to as a "bond-out" chip, and necessarily has associated with it a requirement of a processor design team. From a practical standpoint, the bond-out approach is generally a very expensive alternative not only from a financial standpoint, but likewise from a time and human resources standpoint.
From the foregoing it is observed that while the first basic approach involving the monitoring of the signals from the central processing unit functions in a manner transparent to programs which the central processing unit may be executing, such an approach provides very limited information regarding the particular operations occurring internally to the central processing unit.
In a similar manner, it is observed that while the second basic approach involving using the central processing unit to monitor itself does provide more detailed information regarding the internal operations of the central processing unit, such an approach has the disadvantage of disturbing the environment in which programs execute within the central processing unit.
In addition to the foregoing observations, currently available alternatives to achieve visibility of internal processor status present serious practical implementation limitations.